tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r 2 8 - pin 6 x 6 mm leadless smt pa ckage applications ? 3g / 4g wireless infrastructure ? repeaters ? small cells ordering information part no. description TQC9312 3. 3 - 3.8 ghz d vga TQC9312 - pcb fully assembled evaluation board includes usb control board standard t/r size = 2500 pieces on a 13? reel. general description the TQC9312 is a digital variable gain amplifier (dvga) featuring high linearity over the entire gain control range. this amplifier module integrates two gain blocks, a digital - step attenuator (dsa), and a hi gh linearity ? w amplifier. the module has the added feature of integrating all matching components, bias chokes and blocking capacitors. the internal 6 - bit dsa provides a 31.5 db gain control range in 0.5 db steps, and is controlled with a serial periphe ry interface (spi tm ). the TQC9312 features variable gain from 9 db to 4 0 db at 3 .5 ghz, +4 4. 5 dbm output ip3, and +2 7. 8 dbm p1db. the module operates from a single +5v supply and is available in a compact 28 - pin 6x6 mm leadless smt package. the TQC9312 is pin compatible with the tqm8 7 900 8 ( 1.5 - 2.7 ghz, 0.5w p1db ) and tqm879006 a (1.4 - 2.7ghz, 0.25w p1db ). this allows one to size the right type of device for s pecific system level requirements as well as making the dvga family ideal for applications where a common pcb layout is used for different frequency bands. functional block diagram le data clk nc gnd rfin gnd 1 2 3 4 5 6 7 21 20 19 18 17 16 15 gnd gnd gnd gnd gnd rfout gnd 28 27 26 25 24 23 22 gnd gnd gnd gnd gnd nc 8 9 10 11 12 13 14 gnd gnd gnd gnd gnd dsa amp1 backside pad gnd s p i dc biasing matching dc biasing vcc_ amp1/ amp2 vcc_ amp3 vcc_ spi amp3 amp2 matching product features ? ? 4 0 db gain (min attenuation state) at 3 .5 ghz ? 31.5 db gain range in 0.5 db steps ? +4 4. 5 dbm output ip3 ? +2 7. 8 dbm output p1db ? fully internally matched module ? integrated blocking capacitors, bias inductors ? 3 - wire spi tm control programming pin configuration pin no. label 1 le 2 data 3 clk 4, 22 nc 6 rfin 8 vcc_amp1 ?/?amp2 ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r recommended operating conditions parameter min typ max units v cc (pins 8, 14, 28) +4.75 +5 .0 +5.25 v case temperature ? absolute maximum ratings parameter rati ng storage temperature ? rf input power, 50,t = electrical specif ications test conditions : v cc =+5 v, v cc- spi = +5v, temp= +25c, 50 system, maximum gain state parameter conditions min typ max units operational frequency range 3300 3800 mhz test frequency 3 50 0 mhz gain 3 7 40 4 3 db gain control range 0.5 d b step size 31.5 db attenuation accuracy 3 wire spi, major states (0. 5 + 8 % of atten. setting) max db control interface 3 - wire spi 6 bit s input return loss 1 5 db output return loss 1 7.4 db output p1db +2 7 . 8 dbm output ip3 pout = +11 dbm /tone, ? ? ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r TQC9312 - pcb evaluation board fb1 fb2 c1 c2 u1 j3 j1 j1 j1 j2 j2 j2 c4 spi_le gnd spi_vcc gnd vcc_amp1/ amp2 spi_data spi_clk nc gnd rf_in c1 0 ? gnd gnd gnd gnd gnd nc gnd gnd gnd gnd gnd gnd rf_out c2 0 ? gnd gnd gnd gnd vcc_amp3 c8 0.1uf j2 rf output j1 rf input j3-1 j3-2 j3-3 j3-4 j3-5 j3-6 j3-7 j3-8 j3-9 j3-10 j3-11 j3-12 j3-13 j3-14 j3-15 j3-16 j3-19 j3-17 j3-18 j3-20 spi_vcc data clk le vcc_amp gnd gnd u1 6x6_ 28pin c4 10 uf fb1 0 ? fb2 0 ? r1 0 ? j5 +5v note s: 1. see evaluation board pcb information section for material and stack - up. 2. all components are of 0603 size unless stated otherwise. 3. see serial control interface section f or spi timing diagram . 4. 0 ? jumpers may be replaced with copper traces in the target ap plication layout. 5. different ground pins are used for spi (digital) and analog supply voltages. 6. the primary rf microstrip characteristic line impedance is 50 ?. 7. the single power supply is used to provide supply voltage to amp1 , amp2 and amp 3. typical perf ormance ? test conditions unless otherwise noted: v cc = + 5 v , i cc = 28 5 ma, temp= 25 c , 50 system parameter typical value units frequency 3300 3400 3500 3600 3700 3800 ghz gain 40.1 40 39.8 40. 3 40.7 41.3 db input retu rn loss 17 1 7.8 1 5 1 2 . 6 12.6 14 db output return loss 17 17 .5 1 7.4 1 7.4 15.6 14.8 db output p1db +28.3 +28 .2 +27.8 +27. 5 +27.1 +26.7 dbm output ip3 (pout=+11 dbm/tone, ?f =1 mhz) bill of material ? TQC9312 - pcb r eference des. value description manufacturer part number u1 3.5 ghz ? w dvga triquint TQC9312 c8 0.1 uf cap, chip, 0603, 16v, x7r, 10% various c 4 10 uf cap, chip, 0603, 6.3v, x5r, 20% various c1, c2, fb1, fb2 0 ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r typical performance plots ? TQC9312 - pcb test conditions unless otherwise specified : v cc =+5 v, i cc = 28 5 ma, temp= +25c, 50 system 35 37 39 41 43 45 3300 3400 3500 3600 3700 3800 s(2,1) (db) frequency (mhz) gain vs frequency +85 c +25 c ?40 ?40 ?40 0 5 10 15 20 25 30 35 40 45 3300 3400 3500 3600 3700 3800 gain (db) frequency (mhz) gain vs. frequency 31.5 db 16 db 8 db 4 db 2 db 1 db 0.5 db 0 db -30 -25 -20 -15 -10 -5 0 3300 3400 3500 3600 3700 3800 input return loss (db) frequency (mhz) input return loss vs. frequency 31.5 db 16 db 8 db 4 db 2 db 1 db 0.5 db 0 db -25 -20 -15 -10 -5 0 3300 3400 3500 3600 3700 3800 output return loss (db) frequency (mhz) output return loss vs. frequency 31.5 db 16 db 8 db 4 db 2 db 1 db 0.5 db 0 db -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 attenuation error (db) attenuation states atenuation error vs. attenuation states +85 c +25 c ?40 c frequency = 3500 mhz -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 attenuation error (db) attenuation states atenuation error vs. attenuation states 3300 mhz 3500 mhz 3800 mhz 35 40 45 50 55 8 9 10 11 12 13 14 15 oip3 (dbm) pout (dbm) oip3 vs pout 3300 mhz 3500 mhz 3800 mhz temp = 25 c 35 38 41 44 47 50 3300 3400 3500 3600 3700 3800 oip3 (dbm) frequency (mhz) oip3 vs. frequency +85 c +25 c ?40 c pout/tone = 11 dbm 1 2 3 4 5 6 3000 3100 3200 3300 3400 3500 3600 3700 3800 noise figure (db) frequency (mhz) noise figure vs. frequency +85 c +25 c ?40 c 25 26 27 28 29 30 3300 3400 3500 3600 3700 3800 p1db (dbm) frequency (mhz) p1db vs frequency +85 c +25 c ?40 c datasheet: rev c 1 2 - 0 4 - 1 - 4 of 9 - disclaimer: subject to change without notice ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r serial control interface the TQC9312 has a cmos spi tm input compatible serial interface. this serial control interface converts the serial data input stream to parallel output word. the input is 3 - wire (clk, le and sid ) spi tm input compatible. at power up, the serial control interface resets the dsa to the minimum gain state. the 6 - bit sid (serial input data) word is loaded into the register on rising edge of the clk, msb first. when le is high, clk is internally disabled. serial control timing characteristics (test conditions: v cc = +5 v, t emp. =25c) parameter condition min max units c lock frequency 50% duty cycle 2 0 mhz le setup time, t lesup after last clk rising edge 10 ns le pulse width, t lepw 16 ns s erin set - up time, t sdsup before clk rising edge 8 ns s erin hold - time, t sdhld after clk rising edge 8 ns le pulse spacing t le le to le pulse spacing 630 ns propagation delay t plo le to parallel output valid 10 ns serial control dc logic characteristics (test conditions: v cc = +5 v, t emp. =25c) parameter condition min max units input low state voltage, v il 0 0.8 v inp ut high state voltage, v ih 1.8 v cc v input current, i ih / i il on sid, le and clk pins ? s erin control logic truth table timing diagram 6 - bit control word attenuation state clk is internally disabled when le is high msb lsb serin clk le parallel data valid t sdsup t sdhld t lesup t lepw d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 reference : il 1 1 1 1 1 0 0.5 db 1 1 1 1 0 1 1 db 1 1 1 0 1 1 2 db 1 1 0 1 1 1 4 db 1 0 1 1 1 1 8 db 0 1 1 1 1 1 16 db 0 0 0 0 0 0 31.5 db any combination of the possible 64 states will provide an attenuati on of the sum of bits selected . datasheet: rev c 1 2 - 0 4 - 1 - 5 of 9 - disclaimer: subject to change without notice ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r detailed device description the TQC9312 is a 50 ? internally matched digital variable gain amplifier (dvga) featuring high linearity over the entire gain control range. the amplifier module features the integration of two gain block, a digital - step attenuator (dsa), along with a high linearity ? w amp lifier. the module is unconditionally stable. internal blocking capacitors and bias structures keep external parts count to a minimum. the dvga is optimized for band 41. functional block diagram dsa spi matching network dc bias dc bias pin 1 le pin 6 rf in pin 16 rf out pin 2 data pin 3 clk pin 14 v cc pin 8 v cc dc block matching network dc block dc block dc block amp1 amp2 amp3 dc block datasheet: rev c 1 2 - 0 4 - 1 - 6 of 9 - disclaimer: subject to change without notice ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r pin configuration and description le data clk nc gnd rfin gnd 1 2 3 4 5 6 7 21 20 19 18 17 16 15 gnd gnd gnd gnd gnd rfout gnd 28 27 26 25 24 23 22 gnd gnd gnd gnd gnd nc 8 9 10 11 12 13 14 gnd gnd gnd gnd gnd dsa amp1 backside pad gnd s p i dc biasing matching dc biasing vcc_ amp1/ amp2 vcc_ amp3 vcc_ spi amp3 amp2 matching pin no. la bel description 1 le serial latch enable input. when le is high, latch is clear and content of spi control the attenuator. when le is low, data in spi is latched. 2 data serial data input. the data and clock pins allow the data to be entered serially int o spi and is independent of latch state. 3 clk serial clock input. 4, 22 n/c no connect or open. this pin is not connected in this module 6 rfin input, matched to 50 ohms. internally dc blocked. 8 vcc_amp1 / amp2 supply voltage to amp1 and amp2. this pi n is connected internally to bypass capacitors followed by inductor inside the module. 14 vcc_amp3 supply voltage to amp3. this pin is connected internally to bypass capacitors followed by inductor inside the module. 16 rfout output matched to 50 ohms. internally dc blocked. 28 vcc_spi spi and dsa dc supply . this pin is connected to bypass capacitor internally. 5, 7, 9 - 13, 15,17 - 21, 22 - 27 gnd rf/dc ground connection backside pad gnd rf/dc ground connection evaluation board pcb information triq uint pcb 1 120739 material and stack - up 1 oz. cu bottom layer nelco n-4000-13 core nelco n-4000-13 1 oz. cu top layer 1 oz. cu inner layer 1 oz. cu inner layer 0.062" 0.006" finished board thickness 0.014" 0.014" microstrip line details: width = .030?, spacing = .036?. datasheet: rev c 1 2 - 0 4 - 1 - 7 of 9 - disclaimer: subject to change without notice ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r package marking and dimensions marking: part number ? TQC9312 year/week code ? yyww cccc assembly code ? aaxxxx n otes : 1. all dimensions are in millimeters. angles are in degrees. 2. except where noted, this part outline conforms to jedec standard mo - 270, issue b (variation dae) for extra thin profile, fine pitch, internal stacking module (ism). 3. dimension and tolerance formats conform to asme y14.4 m - 1994. 4. the terminal #1 identifier and terminal numbering conform to jesd 95 - 1 spp- 012. 5. co - planarity applies to the exposed ground/thermal pad as well as the contact pins. 6. package body length/width does not include plastic flash protrusion across mold part ing line. pcb mounting pattern n otes : 1. all dimensions are in millimeters. angles are in degrees. 2. use 1 oz. copper minimum for top and bottom layer metal. 3. vias are required under the backside paddle of this device for proper rf/dc groun ding and th ermal dissipation. we recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10?). 4. ensure good package backside paddle solder attach for reliable operation and best electrical performance. ? 201 4 triquint www.triquint.com
tq c9312 3. 3 ? 3.8 ghz ? ? w digital variable gain amplifie r product compliance information esd sensitivity ratings caution! esd - sensitive device esd rating: 1c value: passes 1000v to < 2000v test: human body model (hbm) standard: jedec standard jesd22 - a114 esd rating: c3 value: pa sses 1000v test: charged device model (cdm) standard: jedec standard jesd22 - c101 solderability compatible with both lead - free (260 c max. reflow temp.) and tin/lead (245 c max. reflow temp.) soldering processes. package lead plating: electrolytic p lated au over ni rohs compliance this part is compliant with eu 2002/95/ec rohs directive (restrictions on the use of certain hazardous substances in electrical and electronic equipment). this product also has the following attributes: ? lead free ? haloge n free (chlorine, bromine) ? antimony free ? tbbp - a (c 15 h 12 br 4 0 2 ) free ? pfos free ? svhc free msl rating msl rating: level 3 test: +260 c convection reflow standard: jedec standard ipc/jedec j - std - 020 contact information for the latest specifications , additional product information, worldwide sales and distribution locations, and information about triquint: web: www.triquint.com tel: +1.503.615.9000 email: info - sales@ triquint .com fax: +1.503.615.8902 for technical questions and application information: email: sjcapplications.engineering@t riquint .com important notice the information contain ed herein is believed to be reliable. triquint makes no warranties regarding the information contained herein. triquint assumes no responsibility or liability whatsoever for any of the information contained herein. triquint assumes no responsibility or liability whatsoever for the use of the information contained herein. the information contained herein is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the user. all information cont ained herein is subject to change without notice. customers should obtain and verify the latest relevant information before placing orders for triquint products. the information contained herein or any use of such information does not grant, explicitly o r implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. triquint products are not warranted or authorized for use as crit ical components in medical, life - saving, or life - sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. datasheet: rev c 1 2 - 0 4 - 1 - 9 of 9 - disclaimer: subject to change without notice ? 201 4 triquint www.triquint.com
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